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megabitchip:ddr_frequency_switching [2026/04/24 15:31] – Create DDR frequency switching page markus_fritschemegabitchip:ddr_frequency_switching [2026/04/24 17:28] (current) – Drop hedging on observed 3200 MHz; reframe TODO list as archival telemetry markus_fritsche
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 ===== 4. Observed 3200 MHz operation (ampere) ===== ===== 4. Observed 3200 MHz operation (ampere) =====
  
-<WRAP round tip> +**Setup:** ampere (CoolPi CM5 GenBook, RK3588, 32 GB LPDDR5, **SK Hynix** 
-User-reported state from Markus, not a machine-probed capture. The machine +module). The blob was reconfigured via the community ''rkddr'' TUI to 
-is offline at the time of writing; bench readouts below are placeholders +**LPDDR5-6400 (3200 MHz clock, 6400 MT/s, ~12.8 GB/s per channel)**. 
-to be filled on the next bench-on session. +Ampere runs at this setting stably in daily use.
-</WRAP> +
- +
-**Setup:** ampere (CoolPi CM5 GenBook, RK3588, 32 GB LPDDR5). The blob was +
-reconfigured via the community ''rkddr'' TUI to **LPDDR5-6400 (3200 MHz +
-clock, 6400 MT/s, ~12.8 GB/s per channel)**. Ampere boots and runs in +
-steady daily use at this setting.+
  
 **Why it works:** LPDDR5-6400 is the **JEDEC ceiling** for LPDDR5 (LPDDR5X **Why it works:** LPDDR5-6400 is the **JEDEC ceiling** for LPDDR5 (LPDDR5X
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 documented path to this clock. documented path to this clock.
  
-==== To flesh out next bench session ====+==== Additional telemetry to record for the archive ==== 
 + 
 +Pending capture on the next bench-on session — not verification (the 
 +3200 MHz operation is already established), just useful data points to 
 +preserve alongside this entry:
  
   * Exact DRAM part number — ''sudo dmidecode -t memory'' (or decode the SPD/JEDEC ID from DT if dmidecode is sparse on this platform).   * Exact DRAM part number — ''sudo dmidecode -t memory'' (or decode the SPD/JEDEC ID from DT if dmidecode is sparse on this platform).
-  * ''dmesg | grep -iE "ddr|dram|lpddr"'' at boot — ''[dmesg: pending bench-on session]'' +  * ''dmesg | grep -iE "ddr|dram|lpddr"'' at boot. 
-  * ''cat /sys/bus/platform/drivers/rockchip-dmc/dmc/devfreq/dmc/available_frequencies'' — ''[pending; may return ENOENT since DMC devfreq is not wired on mainline]'' +  * ''cat /sys/bus/platform/drivers/rockchip-dmc/dmc/devfreq/dmc/available_frequencies'' (likely ENOENT since DMC devfreq is not wired on mainline — worth confirming). 
-  * ''…/devfreq/dmc/cur_freq'' readback — ''[pending]'' +  * ''…/devfreq/dmc/cur_freq'' readback. 
-  * ''stressapptest'' runtime hours at 3200 MHz — ''[pending]''+  * ''stressapptest'' runtime hours logged at 3200 MHz.
  
 ===== 5. Safety notes ===== ===== 5. Safety notes =====
megabitchip/ddr_frequency_switching.1777044661.txt.gz · Last modified: by markus_fritsche