Differences

This shows you the differences between two versions of the page.

--- megabitchip:start [2026/04/21 20:32] – external edit 127.0.0.1
+++ megabitchip:start [2026/04/25 21:05] (current) – via XML-RPC markus_fritsche
@@ Line 3: / Line 3: @@
 Running index for the **MegabitChip** workstream — reverse-engineering
 and source-rebuilding the RK3588 DDR init blob
-(''rk3588_ddr_lp4_1848MHz_lp5_2112MHz_v1.19.bin'') with the goal of
+(&#039;&#039;rk3588_ddr_lp4_1848MHz_lp5_2112MHz_v1.19.bin&#039;&#039;) with the goal of
 producing a **buildable, working DDR blob** — a behavioural equivalent
 under the reachability + MMIO-trace contract, not bit-identical
@@ Line 16: / Line 16: @@
   * **MMIO-diff: 3173 / 3173 writes byte-identical** (vendor ↔ rebuilt, happy-path LP5 cold boot).
   * **Splicer**: 104 candidates / 85 spliced / 19 skip-larger / 0 failed.
-  * **Splicer skip-list**: 1 entry (''154_FUN_de40'', parked behind task #198).
+  * **Splicer skip-list**: 1 entry (&#039;&#039;154_FUN_de40&#039;&#039;, parked behind task #198).
-  * **Audit**: ''make audit'' green across data-symbols + early-return-tail scans.
+  * **Audit**: &#039;&#039;make audit&#039;&#039; green across data-symbols + early-return-tail scans.
-  * **6 silicon-hostile bugs caught pre-flash** in today's extended session across 3 bug classes — see [[megabitchip:2026-04-21_extended|session wrap]].
+  * **6 silicon-hostile bugs caught pre-flash** in today&#039;s extended session across 3 bug classes — see [[megabitchip:2026-04-21_extended|session wrap]].
 ===== Sub-pages =====
@@ Line 24: / Line 24: @@
   * [[megabitchip:simulation_stack|Simulation & verification stack]] — tripwire, training_sim, bitflip sweep, region classifier, audits, splicer
   * [[megabitchip:port_matrix|Port matrix]] — per-function port status for the monster functions
+  * [[megabitchip:ddr_frequency_switching|DDR frequency switching & 3200 MHz on ampere]] — rkbin stock freqs, four switch mechanisms, DVFS entry point, observed LPDDR5-6400 on ampere
+  * [[megabitchip:pinetab2_ddr|DDR frequency switching on PineTab2 / RK3566 (LPDDR4)]] — sibling page for RK3566/LPDDR4, 1056→1332 MT/s verified on ohm, SPL-extraction gotcha, recovery procedures
 ===== Session recaps =====
@@ Line 34: / Line 36: @@
 ===== Observations =====
-> //"Markus' insistence on simulation before flashing paid off. Big time. Again."// — 2026-04-21.
+> //&quot;Markus&#039; insistence on simulation before flashing paid off. Big time. Again.&quot;// — 2026-04-21.
 The tripwire + PC-bucketed diff caught 3 silent NULL-derefs that hid
-behind a green ''mmio_diff 3173/3173'' baseline. ''ld
+behind a green &#039;&#039;mmio_diff 3173/3173&#039;&#039; baseline. &#039;&#039;ld
---unresolved-symbols=ignore-all'' was quietly zero-resolving undefined
+--unresolved-symbols=ignore-all&#039;&#039; was quietly zero-resolving undefined
-''DATA_SYMS'' externs, turning ''adrp+ldr'' into NULL-deref on silicon.
+&#039;&#039;DATA_SYMS&#039;&#039; externs, turning &#039;&#039;adrp+ldr&#039;&#039; into NULL-deref on silicon.
-A second bug class (C early-return skipping vendor's shared-tail RMW)
+A second bug class (C early-return skipping vendor&#039;s shared-tail RMW)
 and a third (port-as-read-only where vendor writes) surfaced the same
 session. All three would have been silicon corruption if flashed.