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====== RK3588 DDR Init Blob — Reverse Engineering & Patching ======

Running log of the RK3588 DDR init blob project: what's been tried, what
worked, what bricked the board, and what the current state is.

**Source:** [[https://git.reauktion.de/marfrit/rk3588-ddr-analysis]]
**Target hardware:** ampere (CoolPi CM5 GenBook, RK3588 + LPDDR5)
**Status 2026-04-15:** v3fb patcher staged, waiting on UART cable and
ampere SPI recovery to bisection-test.

===== Why we're doing this =====

The RK3588 ships with a closed-source binary blob that initialises
LPDDR4/5 memory during early boot. Rockchip provides no source. The blob
contains at least 20 "timeout-less" hardware poll loops — `do while` with
no iteration cap — which is the community-accepted explanation for
sporadic cold-boot failures on otherwise-stable hardware.

Long-term goal: produce a compileable, well-structured C version of the
blob that we can fix bugs in. Short-term goal: add timeouts to the
poll loops so the board fails fast instead of hanging silently.

===== Timeline =====

==== 2026-04-02 .. 04-11: decompilation + first patcher ====

  * Decompiled v1.19 blob with Ghidra 11.3 on oppenheimer (CT131, x86 PVE container on ''data''). 118 functions, ~12 kLOC.
  * Verified Synopsys DWC LPDDR5 multiPHY heritage. Most registers map
    to the DWC PUB databook (CalBusy, DfiStatus, MicroReset, etc.).
  * Identified 20 timeout-less polls, documented in ''BUG_ANALYSIS.md''.
  * **v1 patcher** (''patch_prod.py''): NOP'd the backward branches of
    each poll. Tested in ''ddr_emu2'' (Unicorn emulator) — looked good.

==== 2026-04-11: v1 bricked the board ====

Flashed NOP-patched blob to the GenBook's SPI flash. Cold-boot failed
to bring DRAM up, entered maskrom. Required battery disconnect +
''rkdeveloptool''-based SPI reflash with stock blob to recover.

**Lesson:** NOPping hardware polls on real silicon removes necessary
wait time. The PHY genuinely needs those iterations to settle. A second
opinion from a DDR-focused expert agent ("Mr. Claude Subagent") confirmed
the diagnosis independently.

==== 2026-04-11 .. 04-14: v2 counted-loop trampolines ====

  * Rewrote the patcher (''patch_timeouts.py'', commit 05d0d8e): each
    poll site now jumps to a per-site trampoline appended at the end of
    the blob. The trampoline counts 16384 iterations (~91 µs at
    1.8 GHz), returns to the original error path on timeout.
  * Output: ''rk3588_ddr_v1.19_counted_v2.bin''.
  * Design reviewed by Mr. Claude Subagent — no objections.
  * U-Boot image built, flashed to ampere's SPI.

==== 2026-04-14: v2 ALSO bricked the board ====

This time worse: **power LED did not even come on**, implying the CPU
crashed before the bootrom's LED-setup code ran. No UART banner, no
diagnostics, nothing. Full battery disconnect + maskrom recovery needed.

At this point **design review had twice approved a broken implementation**.
The design was correct; the implementation was not. Something about the
actual encoded trampoline bytes had to be wrong.

==== 2026-04-15: the thorough check that unearthed the bug ====

Rather than guess what was wrong, we **went back to the bytes**:

  - For each of the 16 patch sites, pulled the original loop body from
    ''ddr_conservative_asm.s'' with surrounding context.
  - Hand-disassembled each trampoline from ''rk3588_ddr_v1.19_counted_v2.bin''
    (raw little-endian uint32 decode, not Ghidra).
  - Cross-compared: **does the trampoline execute the same instructions
    as the original loop, in the same order, producing the same CPU flags
    before the branch?**

The answer for 9 of 16 sites: **no**.

The original poll pattern on those sites was:

<code>
LDR   Wx, [Xbase, #off]
AND   Wx, Wx, #mask        ; no flag update
CMP   Wx, #expected        ; sets NZCV
B.cond .retry
</code>

The v2 patcher had logic like:

<code python>
test_inst = None
for off, w in site['body']:
    if off != site['load_offset']:
        test_inst = w
        break
</code>

It copied **exactly one** non-load instruction into the trampoline.
For body=2 sites (''LDR + TST; B.cond''), fine — the TST was copied and
the condition was valid. For **body=3 sites** (''LDR + AND + CMP; B.cond''),
the AND was copied but the CMP was **silently dropped**.

An AND without S-suffix doesn't update flags. The trampoline's ''B.cond''
therefore tested whatever NZCV happened to be set by whatever instruction
last executed before the trampoline was entered → random branch decision
→ CPU jumped to arbitrary offsets → crash before the bootrom LED stage.

**This is a class of bug that design review cannot catch.** Design review
validates "is the algorithm correct?". The algorithm WAS correct (run the
poll body in a bounded loop). The bug was in the encoder: a wrong bound
on how many instructions constitute "the poll body". Only byte-level
hand-verification against the source disassembly surfaces that kind of
off-by-something.

==== 2026-04-15: v3fb (full-body) + bisection harness ====

  * ''patch_timeouts_v3.py'' (commit 694be88) copies the **entire** loop
    body into each trampoline, not just one instruction. Per-site size
    becomes ''4 * (N + 6)'' bytes where ''N'' is body length (28 bytes
    for body=2, 36 for body=3).
  * New ''--sites'' flag: ''all'', ''early'', ''mid'', ''late'', ''none'',
    or index list like ''0,3,5-7''. Site indices stable:
    * ''early'' = sites 0-7, blob offsets 0x07b78..0x07f08 —
      SGRF + PHY firmware state machine. Brick-suspect cluster.
    * ''mid''   = sites 8-10, 0x09124..0x0aaf8 — DfiStatus / training start.
    * ''late''  = sites 11-15, 0x0d154..0x0d378 — UctWriteProt / CalBusy.
  * Three U-Boot SPI images built on boltzmann
    (''~/projects/AMPere/output/''):
    * ''u-boot-rockchip-spi-midlate-fb-8mb.bin'' — patches sites 8-15.
      **First flash candidate** once ampere recovers. If it boots, the
      v2 bug was concentrated in the early cluster (expected).
    * ''u-boot-rockchip-spi-all-fb-8mb.bin'' — patches all 16. The
      production candidate once midlate-fb is validated.
    * ''u-boot-rockchip-spi-early-fb-8mb.bin'' — patches sites 0-7 only.
      Used if mid+late boots but all bricks.

==== 2026-04-15: pre-flash verification ====

Sanity checks before the next flash attempt:

  * **Emulator trace diff (''ddr_emu2''):** stock, midlate-fb, and all-fb
    produce **byte-identical execution traces** for the first 106
    instructions (the reach of the emulator before it bails on unmodeled
    MMIO). Confirms the trampoline append does not perturb pre-site code.
  * **Hand-decoded trampolines for sites 0, 1, 2:** all three preserve
    the full original body, correctly invert the condition for ''B.cond
    .done'', decrement ''W16'' correctly, and encode the right relative
    branch offsets back to the original return point. No encoder bugs.

===== Pending: UART bisection flash plan =====

Once ampere is recovered from its current brick (battery disconnect +
stock SPI reflash via Ohm running ''rkdeveloptool'') **and** the UART
cable is plugged in on ampere's debug header:

  - Flash ''stock'' → capture UART trace (baseline).
  - Flash ''midlate-fb'' → capture. If boots, v2 bug was in early cluster.
  - Flash ''all-fb'' → capture. This is the production candidate.
  - Per-cluster bisection only if needed.

UART wiring: ampere debug header → USB-UART cable → Ohm (PineTab2)
USB-A port → ''picocom -b 1500000 /dev/ttyUSB0''.

SPI recovery ladder on Ohm (requires ''rkdeveloptool'' Rockchip original,
not Pine64 fork):

<code>
rkdeveloptool ld                                                # confirm maskrom device
rkdeveloptool db ~/projects/AMPere/rk3588_spl_loader_v1.19.113.bin
rkdeveloptool cs 9                                              # select SPI NOR — do NOT skip
rkdeveloptool ef                                                # erase flash
rkdeveloptool wl 0 ~/projects/AMPere/u-boot-rockchip-spi-stock-8mb.bin
rkdeveloptool rd                                                # reboot
</code>

===== Lessons learned =====

  - **NOPping real-hardware polls = brick.** Bounded retries only.
  - **Expert design review is necessary but not sufficient.** A second
    opinion validates the algorithm, not the implementation.
  - **Byte-level verification against source disassembly** is the
    cheapest intervention that catches encoder bugs. It takes an hour,
    costs nothing, and would have caught v2 before flashing.
  - **UART is the only signal source** that's worth iterating against.
    Without it, each flash attempt is a 1-bit oracle that costs a
    screwdriver to read. The moment we have UART the iteration cycle
    goes from hours (brick → disconnect battery → reflash → retry) to
    minutes (flash → read UART → tweak → flash).

===== Files of interest =====

  * ''boltzmann:~/projects/AMPere/'' — full build tree (TF-A, OP-TEE, u-boot, rkbin)
  * ''boltzmann:~/src/rk3588-ddr-decompiled/'' — analysis artifacts, patchers, emu
  * ''ohm:~/projects/AMPere/'' — recovery kit (rkdeveloptool + stock SPI image + loader)
  * [[https://git.reauktion.de/marfrit/rk3588-ddr-analysis]] — public source of truth

==== 2026-04-15 evening: UART connected, three bricks, one silent build bug ====

Long session. Meitner was commissioned as a dedicated x86 flasher workbench
(ThinkPad T430, Debian 13 trixie, XFCE, aarch64 cross-toolchain, rkbin, lmcp
service on :8080) and brought online as the first real consumer of the
''marfrit-packages'' Debian repo.

With a flasher in place the brick-recover cycle drops to ~60 s:

<code>
sudo rkdeveloptool ld
sudo rkdeveloptool db rk3588_spl_loader_v1.19.113.bin
sudo rkdeveloptool cs 9          # SELECT SPI NOR — forgetting = writes eMMC
sudo rkdeveloptool ef
sudo rkdeveloptool wl 0 <image>
sudo rkdeveloptool rd
</code>

Bonus observation: when SPI holds a non-empty but non-bootable image,
the RK3588 bootrom falls back to maskrom on the next power cycle — no
pinhole button needed. Cleanly erased SPI (''rkdeveloptool ef'' with nothing
written) instead falls through to eMMC, which still has a working u-boot
+ Debian — effectively a "two strikes before you're really bricked" safety net.

=== The UART rig ===

The GenBook debug header turned out to be a **4-pin 1.0 mm Chinese-brand
connector**, NOT JST SH. Amazon's "JST SH" cables are too tall
(2.1 mm housing vs. the header's ~1.3 mm depth). Happily, the **x86 GenBook
variant's internal fan cable uses the same connector shell** — one
sacrificed fan cable = one working UART pigtail. Cable design gripe: V+
and GND were crimped next to each other, so one loose dupont sleeve
could short 3.3 V into GND.

Pin voltages (measured on a running stock GenBook):

^ Silkscreen ^ Idle voltage ^ Function ^ Wire colour (this donor cable) ^
| GND | 0 V | GND | Black |
| V+ | 3.3 V | VCC-out rail (''SKIP'', not a signal) | Purple |
| TX | 1.8 V | GenBook TX → Tigard RX | Grey |
| RX | ~0 V floating | GenBook RX ← Tigard TX | White |

That's **asymmetric-voltage UART**: TX is raw 1.8 V PMUIO, RX has a
board-side level shifter to 3.3 V. Tigard at **1.8 V** reads the 1.8 V
TX cleanly; driving RX may need 3.3 V — we didn't need to drive in this
session so 1.8 V stayed.

**Tigard UART lives on Channel A** → ''/dev/ttyUSB0'', not B. Also, set
''echo 1 > /sys/bus/usb-serial/devices/ttyUSB0/latency_timer'' and use
''dd if=... bs=1'' — ''cat > file'' silently block-buffers at 4 KB and
will lose a short boot banner.

Known-good boot captured from stock:

<code>
DDR ff1a08bde6 typ 25/04/21-14:31.26,fwver: v1.19
ch0 ttot6
ch1 ttot6
ch2 ttot6
ch3 ttot6
LPDDR5, 2112MHz
channel[0] BW=16 Col=10 Bk=16 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=8192MB
(×4 channels = 32 GB)
</code>

That banner is the oracle: if patched variants produce it, DDR trained; if
silent, TPL hung.

=== The three-brick bisection ===

With UART and fast reflash in place we tested the v3fb variants back-to-back:

^ Image ^ Sites patched ^ Boot LED ^ UART ^
| stock-8mb | none | on | full banner, SDDM |
| all-fb-8mb | 0..15 | **OFF** | 5 B noise |
| midlate-fb-8mb | 8..15 | **OFF** | 6 B noise |
| early-fb-8mb | 0..7 | **OFF** | 6 B noise |

Every patched variant failed with the **same symptom**, regardless of which
cluster of poll sites was patched. That rules out site-specific encoder
bugs — it's systemic.

=== The real root cause: u-boot built a blank idbloader ===

Byte-diff of stock vs. patched SPI images revealed the smoking gun:

  * stock SPI at offset ''0x8000'' contains the RKNS wrapper magic (''52 4b 4e 53''), then ~57 % non-''0xFF'' content through 0x60000 — real SPL, TPL, DTB.
  * **patched SPI at 0x8000 is ''0xFF FF FF FF''**. The **entire idbloader region (0x8000..0x60000, 352 KB) is pure erase pattern.** Zero content.

So when the v3 patcher appended 548 bytes of trampolines (DDR blob grew
76,704 → 77,252 bytes), u-boot's ''mkimage -T rkspi'' **silently failed
to produce an idbloader**, and binman padded the empty slot with ''0xFF''
without flagging an error. Build "succeeded" but produced a brick-ready
image. The final SPI had u-boot proper at 0x60000 but no loader
in front of it — bootrom reads garbage at 0x8000, can't find a valid
boot path, never gets far enough to light the power LED. It's not an
eMMC-fallback scenario either because the SPI isn't cleanly erased
(there's valid-looking content further in).

**Bottom line: the v3 trampoline bytes were probably fine. We just never
got to execute them.**

=== Pre-flash gate: spi_check.py ===

Committed to the gitea repo:
[[https://git.reauktion.de/marfrit/rk3588-ddr-analysis|rk3588-ddr-analysis]]
commit ''3a90236''.

''spi_check.py'' statically parses the RKNS wrapper at 0x8000 and the
payload region's non-''0xFF'' content. No emulation, purely byte-level.

<code>
$ python3 spi_check.py u-boot-rockchip-spi-stock-8mb.bin
OK  RKNS wrapper present at 0x8000
    payload region 0x8000..0x60000:  205151/360448 non-0xFF bytes (56.9%)
PASS: image looks structurally sound. Safe to flash.

$ python3 spi_check.py u-boot-rockchip-spi-all-fb-8mb.bin
FAIL: no RKNS wrapper at 0x8000: got 0xffffffff. idbloader was not
produced — silently-failed mkimage during u-boot build.
</code>

Wired into ''build_uboot_stock.sh'' and ''build_uboot_rock5itx.sh'' as the
final post-build action. Any build that silently fails mkimage now exits
non-zero instead of producing a brick-ready file. Phase 1 of the broader
"test harness" task.

=== Phase 2 queued: bootrom-level QEMU emulation ===

The user's observation during the post-mortem: a QEMU run of the full SPI
image from bootrom entry, with stubbed MMIO (''return 0'' / ''return 0xFFFF'' /
per-address lookup) would have caught both today's empty-idbloader bug
**and** the earlier v2 counted_v2 CMP-drop brick without touching hardware.
Extending ''ddr_emu2.c'' to accept an SPI image, parse the idbloader header,
and execute the TPL with stubbed MMIO is queued as the next harness layer.
Every real-hardware flash should be gated behind "bootrom emu says it loads"
before it ever reaches ''rkdeveloptool''.

=== Next steps ===

  - Rebuild a patched variant with verbose build logging; identify the
    exact ''mkimage -T rkspi'' rejection reason (size limit? validation check?
    alignment?). Two fix paths: (a) grow whatever size limit rejects the
    patched TPL, (b) compress trampolines into blob dead-space so the
    blob stays ≤ stock size and sidesteps the build pipeline entirely.
  - Extend ''ddr_emu2.c'' per above.
  - Pretty-print GenBook UART trace so the DDR-phase output becomes
    comparable across variants (offset-aligned, timestamp-normalised).

===== Updated files of interest =====

  * ''boltzmann:~/projects/AMPere/'' — build tree (TF-A, OP-TEE, u-boot, rkbin); ''build_uboot_*.sh'' now gated by spi_check.
  * ''boltzmann:~/src/rk3588-ddr-decompiled/'' — analysis artifacts, patchers, emu, **''spi_check.py''** (new).
  * ''boltzmann:~/boltzmann-spi-backup-16M.bin'' — known-good UEFI dump of boltzmann's own SPI before we touch it. Mirrors at ''hertz:~/saving_private_boltzmann/'' and ''meitner:~/boltzmann-spi/''. SHA-256 ''d7a58743…''.
  * ''meitner:~/ampere/'' — all four GenBook SPI images (stock + 3 v3fb variants).
  * ''meitner:~/rkbin/'' — full rkbin tree + built ''rk3588_spl_loader_v1.19.113.bin'' for maskrom ''db''. rkdeveloptool v1.32 built from ''github.com/rockchip-linux/rkdeveloptool'' installed at ''/usr/local/bin/rkdeveloptool'' (the Rockchip stock one doesn't recognise 350b PID and lacks ''cs'').
  * ''ohm:'' — mothballed; meitner is the new flasher workbench.
  * [[https://git.reauktion.de/marfrit/rk3588-ddr-analysis]] — source of truth (pushed over HTTPS+token; boltzmann's SSH key is ''mfritsche@hawking'' fingerprint ''SHA256:LaXfAhn9IH4Hm/MF4BSCW/bxRESeijNybfdL9lNiyKc'', needs to be added in Gitea Settings to enable SSH push).

//Last updated: 2026-04-15 evening//



===== 2026-04-15 (late evening): bootrom emulator + gitea SSH + PineBuds side-quest =====

==== Bootrom emulator delivers ====

Built ''boltzmann:~/src/rk3588-ddr-decompiled/blob_emu.py'' to emulate
the DDR init blob in Unicorn end-to-end:

  * Loaded **position-correct** at ''0xFF001000'' (the bootrom TPL slot —
    blob has an integrity check at entry that compares
    ''(BL_return_addr & 0xFFFFFF00) == 0xFF001000''; loading at 0 makes
    it crash before it does anything useful).
  * **MSR/MRS sysreg skip** via ''UC_HOOK_INTR'' catch + bit-decode +
    ''PC += 4'' continue. Without this, the first ''MSR DAIFclr, #0xF''
    in the prologue triggers ''UC_ERR_EXCEPTION'' and Unicorn stops.
  * **DesignWare DW_apb_uart shim** at ''0xFEB50000'': stubs LSR (+0x14
    = ''0x60'' = THRE|TEMT) and USR (+0x7C = ''0x02'' = TFE), captures
    THR writes (+0x00) into a buffer.
  * Result: emulator prints byte-identical banner to real hardware:
    ''DDR ff1a08bde6 typ 25/04/21-14:31.26,fwver: v1.19''.
  * Stock and **all three v3fb variants** produce identical output
    under both ''--stub 0x00'' and ''--stub 0xFF''. Strong regression
    gate: any patch that breaks the blob's flow now breaks the emu
    output before it touches silicon.
  * Combined with ''spi_check.py'' (RKNS-wrapper validator) the
    pre-flash gate is now two-layered: structural (idbloader present)
    + functional (TPL executes to UART banner).

==== Gitea SSH on port 2222 ====

Gitea container's built-in Go SSH server listens on its **own**
port 2222 inside the container. Externally exposed via incus proxy
device on nc:

  incus config device add gitea ssh-proxy proxy \
       listen=tcp:0.0.0.0:2222 connect=tcp:10.203.71.197:2222

boltzmann's ''id_ed25519'' (fingerprint
''SHA256:ZACfzNBRCWzDjxYaYveQUWoTGZ7cPuw4ynTohxXOsW8'') registered
to user ''marfrit'' via API. Verified end-to-end:

  GIT_SSH_COMMAND="ssh -p 2222" git ls-remote \
       ssh://gitea@git.reauktion.de:2222/marfrit/rk3588-ddr-analysis.git
  → e20563e2…  HEAD
  → e20563e2…  refs/heads/main

Diagnostic note: ''ssh -T gitea@…'' shows ''Permission denied
(publickey)'' but Gitea logs ''Successfully authenticated'' immediately
followed by ''ssh: no auth passed yet''. That's a Go x/crypto/ssh
teardown warning fired when the client closes the channel before opening
a session — harmless, real ''git'' operations work. Don't chase it.

All boltzmann remotes flipped from HTTPS+token to SSH. Token
''95745a345f9c1ddd436a9146f299083f7bc37a51'' retired from URLs.

==== Side quest: PineBuds Pro PR #122 ====

Ralim's review of PR #122 ([[https://github.com/pine64/OpenPineBuds/pull/122]])
asked for the average-coefficient header. Closed the loop:

  * Added ''config/suggested_anc_gains.h'' with three named presets
    (''MODERATE'' / ''AGGRESSIVE'' / ''CONSERVATIVE'').
  * Cherry-picked ''ef606_average_coefficients.h'' (factory IIR coeffs).
  * Made mode0 FF/FB ''total_gain'' configurable via build flag:
    ''-DCFG_ANC_GAIN_AGGRESSIVE'' (FF=700/FB=500),
    ''-DCFG_ANC_GAIN_CONSERVATIVE'' (FF=300/FB=200),
    no flag = MODERATE (FF=500/FB=350) — the user-friendly default.
  * Personal branch on **gitea** (''marfrit/openpinebuds''),
    not the github fork: ''CFG_ANC_GAIN_AGGRESSIVE'' = "dial to 11".

==== Memory addition ====

''feedback_commit_to_real_work.md'' — when asked for a tool that sounds
like a few hours of work, don't pre-shrink it into 20 minutes and pitch
the weak version. Build the requested thing. Provoked by: I tried to
ship ''blob_emu.py'' as a "128-instruction smoke test that returns and
declares victory". User: //"You really try to get around this emulation
endeavour, do you?"//. One more hour later, the full emu printed the
banner.

//Last updated: 2026-04-15 late evening//


===== 2026-04-15 late night: counted-loop v3 is cold-boot-broken =====

**Project-defining finding.** The counted-loop trampoline approach (any counter
value we tested — 16 Ki, 1 Mi, 16 Mi iterations) **cannot** replace the stock
blob's infinite polls for the PHY firmware handshake that fires during F1
frequency retrain on the GenBook RK3588. All-evening bisection turned out to be
warm-PHY illusion; cold-boot control experiments at the end revealed that only
stock cold-boots reliably.

==== The warm-PHY trap ====

Every "known-good" baseline earlier in the evening (''stock'', ''early'',
''midlate'', ''0-8'' through ''0-11'') was tested via ''rkdeveloptool rd'' —
which only fires after ''rkdeveloptool db <spl-loader>'' has pushed its own
SPL into SRAM and **run a full DDR init at 2400 MHz** (visible in UART captures
as the ''DDR ff1a08bde6 typ 25/03/13-15:39:39'' banner preceding our patched
blob's ''typ 25/04/21'' banner). PHY comes up warm and our patched TPL inherits
a trained PHY state where the F1-retrain code path that kills cold boots either
never fires or side-steps site 1.

Cold-tested ''early'' at end of night via RK806 power-off + physical power-on:
**same** ''0:1!2:3:4:'' marker chain as the full-patched variant. Stock cold-tested:
full boot. Bisection was theatre.

==== Diagnostic chain ====

The UART trace rewriter ended up being the tool that cracked it. Each trampoline
emits a unique byte to UART2 (''0xFEB50000'') on entry (''0''–''9'', ''A''–''F''),
a colon on success exit, an exclamation on timeout exit. Typical cold-boot hang tail:

  change to F1: 534MHz
  0:1!2:3:4:
  (hang)

Reads: site 0 succeeded, site 1 **timed out**, sites 2-4 succeeded, then hang
somewhere after site 4 (no trampoline → no marker).

**Site 1 context** (blob offset ''0x7b9c''):

  7b90: orr  w0, w0, #0x2
  7b94: str  w0, [x26, #2948]    ; trigger write (+0xB84)
  7b98: mov  w0, #0x36000000     ; mask = bits 25,26,28,29
  7b9c: ldr  w1, [x26, #2952]    ; body[0]: poll (+0xB88)
  7ba0: bics wzr, w0, w1          ; body[1]: flags
  7ba4: B.NE 0x7b9c              ; (stock: retry forever)

Register ''+0xB88'' is TRM-undocumented — Synopsys DWC PHY PUB space, not
uMCTL2 territory. Stock infinite-poll always succeeds cold; our 1 Mi and 16 Mi
counted loops both time out every time.

==== Likely root cause ====

The PHY firmware state machine is sensitive to either the polling cadence or
the CPU-cycle count before the first LDR. Our trampoline adds a 3-instruction
UART-marker prolog + 1-instruction counter init ≈ 10 cycles of extra latency
before the first read. Stock has zero extra cycles between the ''b'' from the
caller and the ''ldr'' at ''0x7b9c''. If PHY firmware advances state only when
reads arrive inside a specific window, our prolog pushes the first read outside
that window and the handshake silently aborts — no subsequent polling recovers.

Not proven (tonight didn't have time to build a non-trace counter-bump variant
and cold-test it to isolate UART-marker latency from counter-logic latency),
but the evidence pattern fits: stock works, trace-enabled variants fail, counter
size doesn't matter past ~5 ms. Time isn't the independent variable — cycle
count before first read is.

==== Shipping deliverables ====

Tonight we built working tooling. A working **fix** is future work.

  * ''spi_check.py'' — RKNS wrapper + TPL entry-signature gate, run before every flash.
  * ''blob_emu.py'' — position-correct Unicorn emulator at ''0xFF001000'' with MSR/MRS
    skip and DW_apb_uart shim; prints byte-identical DDR banner to real hardware.
  * ''patch_timeouts_v3.py'' — now has ''--counter'' (any MOVZ-encodable imm32) and
    ''--uart-trace'' (per-site entry + success/timeout exit markers).
  * ''build_genbook_sites.sh'' — wrapper for arbitrary site-list subsets.
  * Meitner ''~/ampere/captures/'' — full UART archive of tonight's 11+ variants.

==== Methodology lessons (captured in memory) ====

  * **Warm-PHY illusion** — ''feedback_warm_phy_illusion.md''. Always cold-test the
    baseline BEFORE bisecting any hardware init bug. ''rkdeveloptool rd'' is a
    warm boot, not a cold boot — results are not portable to cold deployment.
  * Linear bisection that looks "too clean for a hard problem" is signal of a
    methodology leak. Tonight's neat ''0-8 boots, 0-9 boots, 0-10 boots, 0-11
    boots, 0-12 hangs'' progression was entirely warm-PHY artifact.

==== Next session direction ====

Re-scope from "patch all 16 timeout-less polls" to "patch only the safe subset":

  - Read each site's body + base register, cross-reference with TRM §2.4 +
    Synopsys DWC uMCTL2 docs.
  - Classify: PHY-firmware handshake polls (DO NOT patch) vs SGRF/firewall/PLL/
    BUS_GRF polls (safe to patch).
  - Rebuild subset patcher, cold-test. If a non-empty safe subset exists, ship that.

Stock stays on the GenBook SPI as the reliable cold-boot variant. Board is
currently running Arch from stock.

//Last updated: 2026-04-15 23:51//


===== 2026-04-16: MVP1 delivered — root cause was reseating =====

The original "board craps out at 2400 MHz" problem that started the entire
MegabitChip project was **hardware, not firmware**. Two physical interventions
resolved it:

  - **Reseating the CM5 module** in its PCIe-style socket → restored LPDDR5
    signal integrity at 2400 MT/s. User confirmed: "Definitely reseating."
  - **Copperfield copper-shim cooling mod** → improved thermal margin at
    elevated temps.

After reseating + swapping to the stock 2400 MHz DDR blob
(''rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.19.bin''), the GenBook cold-boots
reliably at 2400 MHz, survives full kernel compiles at 84 °C avg core temp,
and passes ''memtester'' on 16 GB (previously failed).

==== MVP1 shipped deliverables ====

^ Deliverable ^ Location ^ Status ^
| Unicorn blob emulator | ''boltzmann:blob_emu.py'' | Byte-identical DDR banner |
| SPI pre-flash validator | ''boltzmann:spi_check.py'' | Wired into build scripts |
| UART trace rewriter | ''patch_timeouts_v3.py --uart-trace'' | Entry + exit markers |
| Configurable counted-loop patcher | ''patch_timeouts_v3.py --counter --sites'' | Cold-boot-broken for PHY polls |
| GenBook flash pipeline | ''meitner:~/ampere/'' | 90 s iteration |
| Ghidra LLM auto-renamer | ''oppenheimer:LLMRename.java'' | ~25% yield on fresh projects |
| Cold-boot methodology | ''feedback_warm_phy_illusion.md'' | Lesson captured |
| UART capture archive | ''meitner:~/ampere/captures/'' | 11+ variants |
| 2400 MHz stock GenBook SPI | ''meitner:~/ampere/u-boot-rockchip-spi-2400MHz-stock-genbook-8mb.bin'' | Cold-boot-proven |

==== MVP2 goal ====

Boot from **source-regenerated blob**: matching-decomp all 118 functions →
clang recompile → byte-identical binary → then **modify**. Currently at 1/118
functions matched (''train_phy_block'' at 96%+). Once source exists, the
community can rewrite training algorithms, expose OC knobs, and do things
Rockchip never intended. Question of principle.

//Last updated: 2026-04-16 00:xx//

====== MVP2 session 2026-04-20 — matching-decomp blitz ======

Single session, **1/118 → 33/118 functions matching-decomped**.
Canonical compile line settled + poll-site coverage jumped to 15/16.

===== Canonical compile line =====

<code bash>
clang -O2 -ffreestanding -mgeneral-regs-only \
      [-fno-pic]          # when referencing extern data symbols
      [-fno-builtin]      # when lifting memcpy/memset
      [-fno-unroll-loops] # for small fixed-count loops
</code>

  * **Hard required:** ''-mgeneral-regs-only''. EL3 TPL has no
    FPU/NEON enabled; any ''q0/q1'' vector insn would fault.
    Without the flag, clang's vectorizer replaces byte/word loops
    with 128-bit NEON ldp/stp (observed on FUN_00000ac8: 428 B of
    Neon vs 112 B scalar vendor).
  * ''gcc -O2 -ffreestanding'' stays acceptable; on some small
    helpers (FUN_000027e0) gcc byte-matches vendor where clang
    picks different register allocation.

===== Workspace =====

All lifts live in ''boltzmann:~/projects/AMPere/benchmark/NN_<name>/''
with 5 files each:

  * ''func.bin''  — raw slice from
    ''rkbin/bin/rk35/rk3588_ddr_lp4_1848MHz_lp5_2112MHz_v1.19.bin''
  * ''func.s''    — objdump -D
  * ''reference.c'' — annotated ground truth
  * ''candidate.c'' — clang-friendly source
  * ''GRIND_LOG.md'' — per-function summary + vendor-vs-clang deltas

===== Poll-site coverage: 4/16 → 15/16 =====

^ site ^ containing fn ^ benchmark dir ^ semantic role ^
| 0 | FUN_00007730 | 15_site0_block | PHY train interlock disable |
| 1 | FUN_00007730 | 14_site1_block | DFI shadow handshake (bit 1 / 4-lane ack) |
| 2 | FUN_00007730 | 07_site2_block | Enter Normal operating-mode |
| 3 | FUN_00007730 | 11_site3_block | DDRCTL_DFISTAT bits[2:1] clear |
| 4 | FUN_00007730 | 18_site4_block | Enter Self-refresh |
| 5 | FUN_00007730 | 19_site5_block | Wait selfref_type == auto |
| 6 | FUN_00007730 | 20_site6_block | DFI shadow handshake (bit 0 / 2-lane ack) |
| 7 | FUN_00007730 | 21_site7_block | Exit Self-refresh |
| 8 | FUN_00008b40 | 35_site8_block | Enable auto-ctrlupd + wait Normal |
| 9 | FUN_00009a90 | 40_site9_block | Exit SREF, 2-bit variant |
| 10 | FUN_00009a90 | **pending** | absolute 0xff000024 access — SRAM mirror? |
| 11 | FUN_0000d10c | 05_prep_freq_change | wait PHY state 1 |
| 12-15 | FUN_0000d328 | 04_train_phy_block | PHY training step |

Only **site 10** remains — sits in the 9044-byte FUN_00009a90 monster,
uses an absolute address (not a ch_base + offset) so needs wider
context before extraction.

===== Highlights — what landed this session =====

  * **FUN_00002340** — MR-submit (TRM-verified DDRCTL_MRCTRL0/1/STAT
    registers). Highest-leverage dispatcher callee; every MR write
    in FUN_6c8c (LP4/x) and FUN_6d90 (LP5) goes through this.
  * **FUN_0000337c** — freq→timing LUT. LP5 thresholds 533/800/1600/
    2133 MHz, LP4 thresholds 400/613/1066 MHz. Returns a pointer
    into the blob's 0x11C78/0x11CE0 data-region timing tables.
  * **FUN_00006c8c** (LP4/x) + **FUN_00006d90** (LP5) — MR dispatch.
    6d90 compiled to **exactly 364 B** matching vendor (size-exact).
    Together: 16 MR writes per per-channel-per-rank iteration.
  * **FUN_00000ac8** — memcpy_aligned with same-ptr shortcut and
    8-byte fast path.
  * **FUN_00000b38** — xorshift-seeded buffer hash, seed 0x47C6A7E6
    (DJB-variant with XOR fold).
  * **FUN_00000b88** — ATAGS magic validator, accepts {0,
    0x54410001} ∪ [0x54410050, 0x544100FF].
  * **FUN_00000bd8** — SRAM_BOOT range + overflow validator for
    ATAGS reads (SRAM window 0x1FE000..0x200000, 8 KB).
  * **Print chain closed:**
    - ''FUN_000104b8'' puts (CRLF-expanding)
    - ''FUN_000104f8'' recursive decimal print
    - ''FUN_00001194'' "channel[N] " dispatcher (tail-calls FUN_f60)
  * **Timer chain closed:**
    - ''FUN_00010a38'' udelay via CNTPCT_EL0 + CNTFRQ_EL0
    - ''FUN_00010a70'' system_timer_init (STIMER @ 0xFD8C8000)
  * **Prep/restore freq-change pair** — FUN_d10c save + FUN_d1d0
    restore, with matching save-area offsets 0x238/0x240/0x244/
    0x248/0x24C.
  * **FUN_0000cb44** (1088 B training-timing pack) — **full port**
    from Ghidra decompile. Compiles clean with -Wall -Wextra at
    944 B. The −13 memory-op delta vs vendor is clang's legitimate
    RAM-access coalescing. **Cross-validation under blob_emu.py
    still pending — backlog item #36.**

===== Context-map decoded =====

''FUN_0000d390'' (init_ctx_pointers) writes 25 constants to the
208-byte ctx struct — decoded as the blob's RK3588 physical-address
dictionary:

^ ctx offset ^ value ^ role ^
| 0x00..0x60 (stride 0x20) | 0xF7..0xFA000000 | 4-ch DDR channel bases |
| 0x08..0x68 | 0xFE0C..0x0F0000 | 4-ch CRU-DDR |
| 0x10..0x70 | 0xFD80..0x0C000 | 4-ch DDRPHY (16K stride) |
| 0x18..0x78 | 0xFE00..0x06000 | 4-ch DDRCTL (8K stride) |
| 0x80 | 0xFD58A000 | GRF sideband |
| 0x88 | 0xFD7C0000 | CRU |
| 0x90 | 0xFD59E000 | GRF alt |
| 0x98 | 0xFD586000 | GRF (3rd) |
| 0xA0 | 0xFD587000 | GRF (4th) |
| 0xB8 | 0xFD8D0000 | GRF DDR |
| 0xC0 | 0xFD588000 | GRF (5th) |
| **0xC8** | **0xFD59C000** | **DMC sec_a** (prep/restore + setup sec_table) |
| **0xD0** | **0xFD59D000** | **DMC sec_b** |

Confirms: the secondary-table pointers used in prep_freq_change,
restore_freq_change, and setup_channels point into DMC (Dynamic
Memory Controller) timing-register regions at 0xFD59C000/0xFD59D000
— Rockchip-vendor register islands separate from the uMCTL2 DDRCTL
block.

===== Strings decoded =====

| offset | content |
| 0x10C36 | ''"Magic is not support\n"'' |
| 0x10C4C | ''"Tag is overflow\n"'' |
| 0x10DA4 | ''"unsupported dram type\n"'' |
| 0x113D1 | ''", "'' |
| 0x11491 | ''"MHz\n"'' |
| 0x114E9 | ''"channel["'' |
| 0x114F2 | ''"] "'' |

===== Caveat — to validate before relying on =====

''FUN_0000cb44'' (1088 B, per-channel training-timing pack) is a
full port of the Ghidra decompile. Compiles clean at 944 B. The
−13 memory-op delta vs vendor is clang's legitimate RAM-access
coalescing for a non-volatile struct — post-function RAM state
should match, but **hasn't been cross-validated under blob_emu.py**.

**Backlog item #36** = "Run both vendor and candidate under
blob_emu.py with identical input state (ctx, ch_idx, ch_array_base)
and compare post-function RAM state at ctx+ch_idx*0x6C and
target+0x10..0x24."

===== Backlog staged =====

Next 10 units (tasks #37–46 in session state, of which tasks 37–43
are **complete as of EOD 2026-04-20**):

  * 37 FUN_000104b8 puts ✔
  * 38 FUN_000104f8 print_decimal ✔
  * 39 FUN_00010a38 udelay ✔
  * 40 site-9 poll block ✔
  * 41 FUN_00000e5c freq_log ✔
  * 42 FUN_00010a70 system_timer_init ✔
  * 43 FUN_00002110 dram_type → timing base ✔
  * 44 FUN_0000bf7c (tiny thunk)
  * 45 FUN_000016bc
  * 46 FUN_00002e88

After those, the larger targets still on the shelf:

  * site 10 extraction (FUN_00009a90 body)
  * FUN_000027f8 (508 B, 7730-callee)
  * FUN_00005540 (2636 B monster)
  * FUN_00009a90 non-site-9/10 body (~6500 B remaining)
  * FUN_00008b40 non-site-8 body (~2100 B)

===== Numbers =====

| metric | start of session | end |
| matching-decomp units | 1 | 33 (7 more in-flight tonight) |
| poll-sites covered | 4/16 | 15/16 |
| benchmark directories | 5 | 36+ |
| cumulative bytes of vendor asm lifted | ~104 B | ~6.0 KB |